Method and apparatus for timing management in a converted design

ABSTRACT

Described is a method of converting one representation of a circuit into another. For example, a first network representation adapted for use with an FPGA can be converted into a second network representation adapted for use in a mask-programmable gate array. The method begins with accessing the first network representation, such as a netlist, and identifying signal paths that might be sensitive to race conditions. Representations of delay elements are then inserted into each sensitive signal path. The timing of the modified network representation is then modeled by calculating the delays associated with each signal path. Any differences in the modeled delay values are minimized by modifying one or more of the inserted delay-element representations. In one embodiment, the inserted delay-element representations include stopper cells that maintain the nets to and/or from the delay-element representations. Delay-element representations can therefore be modified without altering the circuit timing of related net segments.

FIELD OF THE INVENTION

[0001] This invention relates to the field of circuit design. Inparticular, the invention relates to a method and apparatus forconverting a programmable-logic-device representation of a circuit intoa second representation of the circuit, such as a representation forimplementing the circuit on a mask-programmable gate array.

BACKGROUND OF THE INVENTION

[0002] Programmable logic devices (PLDS) are a well-known type ofdigital integrated circuit that may be programmed by a user (e.g., acircuit designer) to perform specified logic functions. One type of PLD,the field-programmable gate array (FPGA), typically includes an array ofconfigurable logic blocks (CLBS) that are programmably interconnected toeach other and to programmable input/output blocks (IOBs). Thiscollection of configurable logic may be customized by loadingconfiguration data into internal configuration memory cells that definehow the CLBS, interconnections, and IOBs are configured.

[0003] The ease with which a given logic function can be implementedusing a PLD makes PLDs very inexpensive in small quantities. Incontrast, application-specific integrated circuits (ASICs)are moreexpensive to implement a given design, but less expensive to produce inlarge quantities. Thus, where economies of scale warrant, a vendor maywant to design and implement a logic circuit using a PLD, takingadvantage of the ease of design and the attendant reduction in time tomarket. Then, if economies of scale warrant, the vendor may convert thePLD design into a design specification for another type of integratedcircuit, such as a mask programmed integrated circuit (MPIC). Thisconversion process may be to a simple mask programmed version of thePLD, or a totally different representation.

[0004]FIG. 1 illustrates a system 100 in which a PLD 102 is removed froman IC site 104 and replaced with a new integrated circuit 106 having thesame functionality as PLD 102. PLD 102 conventionally includes acollection of configurable elements 108 that are programmed to performthe functions of a circuit design 110. The new integrated circuit 106, amask-programmable gate array, for example, includes designimplementation logic 112 that also performs the functions of circuitdesign 110.

[0005]FIG. 2 illustrates a method of converting a PLD representation ofcircuit design 110 of FIG. 1 into a second representation for use with adifferent implementation technology (the “target technology”). Beginningwith step 210, a user enters a text or graphic description of circuitdesign 110 using a software tool, such as the ViewDraw™ tool availablefrom ViewLogic, Inc., of Milpitas, Calif. Next, in step 212, thesoftware tool then creates a design description 214. Design description214 may include, for example, a conventional hardware-descriptionlanguage (HDL) or netlist description of circuit design 110.

[0006] PLDs require custom circuit representations suited for use inspecific PLD architectures. Data for implementing design 110 on aspecific PLD is therefore generated at step 215. These data include anew netlist representation 217 of circuit design 110 and a bit-wiserepresentation of circuit design 110, i.e., bitstream 218. Netlist 217and bitstream 218 may be generated using, for example, the XACTsoftware, version 5.0, provided by Xilinx, Inc., having an address at2100 Logic Drive, San Jose, Calif.

[0007] Next, in step 220, the information for programming the group ofconfigurable elements 108 in PLD 102 is parsed from netlist 217 and/orbitstream 218. The parsing step organizes the data in bitstream 218 toproduce an element identifier 221 and element programs 225. Elementidentifier 221 uniquely identifies each programmable element in the newintegrated circuit 106 and element programs 225 specifies theconfiguration of those programmable elements. For example, one set ofbits from bitstream 218 programs a Configurable Logic Block (CLB) of anFPGA, another set of bits, from the same bitstream 118, identifies andprograms an Input/Output Block (IOB) of the FPGA, while yet another setof bits configures the interconnections between the CLB and the IOB.

[0008] A pre-compile representation 237 of the PLD representation ofcircuit design 110 is built during step 230. Step 230 may includegenerating an HDL file that includes several instances of differentgeneral models. Each instance of a general model corresponds to adifferent type of configurable element in PLD 102. Element identifier221 identifies the type of general model to use (e.g., an IOB generalmodel, a CLB general model, or an interconnection element general model)for each programmable element in new integrated circuit 106. Thecorresponding element program 225 defines some parameters for theinstance of the general model, e.g., which circuits to include in agiven instance of a general model.

[0009] At step 240, a compiler converts the pre-compile representation237 into a post-compile representation 247. The pre-compilerepresentation 237 includes an accurate representation of circuit design110 in PLD 102. However, pre-compile representation 237 also includes anumber of unnecessary structures. For example, if a given instance of aninput/output block general model is defined as an input port (theparameters to that instance define the instance as an input port), thenthe structures in that instance that implement output functions are notnecessary. The compile step 240 removes the unnecessary structures. Inone embodiment, the compiler is a Synopsys Design Compilers, availablefrom Synopsys, Inc., of Mountain View, Calif. The compiler uses the afabrication technology library 242 for the target technology to generatethe post-compile representation 247.

[0010] At step 250, a place and route tool is used to place and routethe post-compile representation 247 in the target technology. Anexemplary place and route tool is Gate Ensemblem from Cadence Systems,Inc., of Santa Clara, Calif. Step 250 produces a specification forfabrication 255, typically a magnetic tape written in CaltechIntermediate Format (CIF, a public domain text format) or GDSII Stream(formerly also called Calma Stream, now Cadence Stream). At step 260,from the specification for fabrication 255, a semiconductor foundrymanufactures the new integrated circuit 106 that functions as specifiedby circuit design 110.

[0011] For a detailed description of exemplary methods and apparatus forconverting PLD circuit designs for use in other circuit technologies,see U.S. Pat. No. 5,815,405, entitled “Method and Apparatus forConverting a Programmable Logic Device Representation of a Circuit intoa Second Representation of the Circuit,” by Glenn A. Baxter, issued Sep.29, 1998, which is incorporated herein by reference.

[0012] The design engineer responsible for converting a PLD design foruse with a target technology must verify the operation of the converteddesign to ensure that the new implementation is functionally equivalentto the PLD implementation. This is particularly important because thefabrication technology used to fabricate the new integrated circuit 106affects the speed of the device. Thus, even though all of circuit design110, as implemented in the PLD 102, is completely defined in designimplementation logic 103, the speed of the new integrated circuit 106may be significantly different than that of PLD 102. These speeddifferences may result in malfunctions because of race conditions andother timing-related problems.

[0013]FIG. 3 depicts a conventional clock tree 300 used to illustratepotential timing problems in converted designs. Clock tree 300 includesa net 310 that distributes a clock signal on terminal TCLK to a numberof clock branches A-M. Each of clock branches A-M connects to one ormore destination circuits, as indicated by the annotations provided foreach clock branch. For example, clock branch E connects to 17destination circuits.

[0014] One line from clock branch A and another line from clock branch Dconnect to the clock terminals of respective flip-flops 305 and 310,which are exemplary destination circuits. Ideally, clock signalsprovided on clock terminal CLK should arrive at the clock terminals offlip-flops 305 and 310 (and the other destination circuits) atapproximately the same time. Otherwise, time-dependent data can becorrupted. For example, if flip-flop 310 clocks before flip-flop 305,then flip-flop 310 may capture data before that data is available fromflip-flop 305, the result being that flip-flop 310 could containincorrect data.

[0015] Ensuring that each destination circuit receives clock signals atapproximately the same time is difficult because of the myriadcombinations of paths that make up a typical clock tree. These pathsinclude interconnected lines of different lengths and interveningcomponents, therefore each path has some associated delay. The delays ofthe various signal paths within net 310 should therefore be balanced toensure fast, error-free circuit operation.

[0016] The traditional method of balancing signal paths within a givencircuit includes simulating circuit operation and monitoring the resultsat selected circuit nodes for errors. Such errors, combined with anunderstanding of the intended function of the circuit, enable testengineers to identify problem paths. Once the problem signal paths arelocated, the netlist is changed to alter the offending paths. Forexample, if a clock signal arrives too late to capture some data, eitherthe clock signal or the data line can be rerouted to change the relativedelays.

[0017] The trouble with the conventional approach is two fold. First,identifying problem paths by simulating circuit operation requires anintimate knowledge of the logic being implemented. A user must thereforeunderstand the functionality of a given circuit to perform a conversionfrom one circuit technology to another. Second, each signal path of agiven net may be related to others. Thus, rerouting a signal path tosolve one problem can change the delays of many other paths, and therebyintroduce new timing errors. The new errors must, in turn, be corrected,which can introduce still other timing errors. Balancing signal paths istherefore an iterative and often very time-consuming process. What isneeded is a more efficient method of converting one representation of acircuit into another, preferably without requiring those responsible forthe conversion to understand the function of the circuit.

SUMMARY

[0018] The present invention is directed to an efficient method ofconverting one representation of a circuit into another. For example, afirst network representation adapted for use with an FPGA can be easilyconverted into a second representation adapted for use in amask-programmable gate array. The method of the present invention sosimplifies the conversion process that those responsible for theconversion need not have a detailed understanding of the circuit.

[0019] The method begins with accessing the first networkrepresentation, such as a netlist, and identifying signal paths thatmight be sensitive to race conditions. Such signal paths might be anumber of clock or data paths that connect between a signal source and anumber of signal destinations. Representations of delay elements arethen inserted into each sensitive signal path.

[0020] Once delay-element representations are inserted into the networkrepresentation, the timing of the new network representation is modeledby calculating the delays associated with each signal path. Anydifferences in the modeled delay values are minimized by modifying oneor more of the delay-element representations.

[0021] The components of the network representation are placed androuted once the signal paths are sufficiently balanced. The resultingcircuit specification includes additional timing information, allowingthe netlist to be back-annotated with more precise timing estimates. Thetiming of the back-annotated network representation is then modeled onceagain. The delay-element representations may be modified again at thisstage as required to balance the signal paths of interest.

[0022] Conventional routing tools reroute nets associated withcomponents that are modified, removed, or replaced. Modifying delayelements to balance signal paths can therefore initiate a reroute thatintroduces new timing errors. One embodiment of the invention avoidsthis problem by bounding each delay element, on one or both sides, witha place-holding cell, or “stopper cell.” The stopper cells maintain thenets to and/or from the delay elements so that modifying a delay elementdoes not affect the routing to and from the delay element.

[0023] Each stopper cell and delay element introduces some delay intothe associated signal path. In some cases, this delay should be as smallas possible, for example, where the delay associated with a given signalpath should be minimized. In such situations, the present inventionemploys a specialized stopper cell that occupies very little area andintroduces a minimal amount of delay. In one embodiment, thisspecialized stopper cell is a library element that defines a conductivesegment between a pair of ports, and that does not connect to any activecircuit components within the cell. The simple design allows the stoppercell to be made very small, and the conductive segment introduces verylittle signal propagation delay.

BRIEF DESCRIPTION OF THE FIGURES

[0024]FIG. 1 illustrates a system 100 in which a PLD 102 is removed froman IC cite 104 and replaced with a new integrated circuit 106 having thesame functionality of PLD 102.

[0025]FIG. 2 illustrates a method of converting a PLD representation ofcircuit design 110 into a second representation for use with a differentimplementation technology (the “target technology”).

[0026]FIG. 3 depicts a conventional clock tree 300 used to illustratepotential timing problems in converted designs. Clock tree 300 includesa net 310 that distributes a clock on terminal CLK to a number of clockbranches A-M.

[0027]FIG. 4A depicts a clock tree 400 in accordance with the invention.

[0028]FIG. 4B depicts an exemplary non-inverting delay element 415.

[0029]FIG. 4C depicts an exemplary inverting delay element 420.

[0030]FIG. 5A is a flowchart depicting a process 500 of inserting andadjusting delay elements 410A-I to balance clock branches A-M of FIG. 4.

[0031]FIG. 5B depicts a portion of an illustrative log file 509generated in step 508 of FIG. 5A.

[0032]FIG. 6 depicts four exemplary delay elements 601-604.

[0033]FIG. 7A depicts one embodiment of a stopper cell 700 in accordancewith the invention that has a minimal impact on die area and signalpropagation delay.

[0034]FIG. 7B depicts an example of how stopper cell 700 is physicallyinstantiated in a gate array.

[0035]FIG. 7C depicts a stopper cell 720 in accordance with anotherembodiment of the invention.

DETAILED DESCRIPTION

[0036]FIG. 4A depicts a clock tree 400 in accordance with the inventionthat distributes a clock signal on a terminal CLK to a number of clockbranches A-M. Like clock tree 300 of FIG. 3, each of clock branches A-Mis connected to one or more destination circuits (e.g., flip-flops). Forexample, clock branch E connects to 17 destination circuits. Unlike theconventional clock tree 300, however, clock tree 400 includes a numberof programmable delay elements 410A-410I inserted into various netsegments of clock tree 400.

[0037] Delay elements 410A-410I are incorporated into a circuit netlistto define delay-inducing components. Delay elements 410A-410I mightinclude different numbers and sizes of buffers and inverters, forexample. Delay elements 410A-410I can be individually modified inaccordance with the invention to balance the delays associated with eachof clock branches A-M, thereby reducing the total clock skew of clocktree 400.

[0038] Delay elements 410A-410I are so-called “soft macros,” which aregroups of hard library elements incorporated into a circuit netlist.Hard library elements can change position on a die during place androute, but the relative locations of the transistors and wiring insidethe library elements are fixed. In contrast, soft macro contain onlyconnection information, so that the placement and wiring of soft macroscan vary during place and route.

[0039]FIG. 4B depicts an exemplary non-inverting delay element 415, andFIG. 4C depicts an exemplary inverting delay element 420. Delay element415 includes a buffer 425 bounded by a pair of specialized place-holdingcells, or “stopper cells,” 430. Delay element 420 includes an inverter435 and a pair of stopper cells 440. Recalling that conventional routersreroute nets associated with net components that are modified, removed,or replaced, stopper cells 430 and 440 maintain the nets to and/or fromeach delay element 410A-410I when the delay component associated with agiven delay element (e.g., buffer 425) is modified, removed, orreplaced.

[0040]FIG. 5A is a flowchart depicting a process 500 of inserting andadjusting delay elements 410A-I to balance clock branches A-M of FIG. 4.Process 500 starts with post-compile PLD representation 247 (FIG. 2),which is a netlist defining the function of the new integrated circuitimplemented in the target technology. Delay elements 410A-I are added tothis netlist as additional soft macros that represent delay elements(step 504). The resulting netlist 505 is functionally equivalent topost-compile representation 247. An attempt can be made in step 504 tobalance the delays associated with clock branches A-M by usingrelatively fast delay elements to drive heavily loaded clock branchesand relatively slow delay elements to drive lightly loaded clockbranches.

[0041] In step 506, a test program creates simulation vectors forsimulating the clock timing relationships defined in netlist 505.Stimulus file 507 is the result of step 506. Stimulus file 507 containsvectors that cause positive and negative clock transitions at each clockdestination. When simulated in step 508, stimulus file 507 causes clocktiming information to be logged in a log file 509.

[0042] Step 508 is a pre-layout simulation that takes into accountlogic-cell delays and, in some cases, estimated interconnect delays. Inthe example of FIG. 4, the delays associated with each clock destinationare calculated for test vectors applied to clock terminal CLK. Forexample, if each clock destination is the clock terminal of a respectivedestination flip-flop, then test vectors are developed to calculate thetime and state of each destination flip-flop.

[0043]FIG. 5B depicts a portion of an illustrative log-file 509generated in step 508 of FIG. 5A. Each row of log file 509 represents achange in the state of the clock on terminal CLK or of the output of oneor more destination circuit. Each row includes a time stamp (not shown)indicating the time at which one of the data points in the row changedstate. In FIG. 5B:

[0044] 1. column 1, labeled CK, represents the state of clock terminalCLK;

[0045] 2. columns 2-7 represent the output levels from each of the sixdestination circuits (e.g., flip-flops) associated with clock branch A;

[0046] 3. column 8 represents the output level from the one destinationcircuit associated with clock branch B; and

[0047] 4. columns 9-13 represent the output levels from each of the fivedestination circuits associated with clock branch C.

[0048] For ease of analysis, log file 509 is formatted so that alldestinations of a given clock branch (e.g., destinations A1-A7) aregrouped together. Clock branch D is only partially illustrated and theremaining clock branches E-M are omitted for brevity.

[0049] Referring to column one, clock terminal CLK transitions to alogic one at time TCLK. The outputs of the various destination circuitsare monitored (e.g., captured at discrete time intervals) in thesimulation to determine when they change in response to the clock. Thefirst change occurs in column 10 at time C1, so called because it is thefirst instance of a change associated with clock branch C. As timeprogresses, the remaining destinations of clock branch C change at timesC2-C5, two destinations of clock branch D change at times D1 and D2, andone destination associated with clock branch A changes at time A1. Step508 continues until all destinations have changed.

[0050] Log file 509 includes all of the timing information needed toestimate the clock skews associated with each of clock branches A-M.However, such log files are typically very large, often hundreds ofmegabytes, and consequently unwieldy for human operators. Log file 509is therefore simplified in step 510 into the formats illustrated inTables 1 and 2. TABLE 1 MIN MAX MAX- BRANCH EDGE LOADS LCOL RCOL Δ Δ MINA R 6 2 7 7657 8027 370 B R 1 8 8 7761 7761 0 C R 5 9 13 7355 7431 76 DR 13 14 26 7561 7757 196 E R 17 27 43 7983 8101 118 F R 16 44 59 78808357 477 G R 14 60 73 7804 8185 301 H F 8 74 81 7805 7977 172 I R 16 8297 7775 8102 327 J R 17 98 114 7715 8339 624 K F 195 115 309 7594 7940346 L F 5 310 314 7703 8862 1159 M R 3 315 317 7479 7563 84

[0051] Table 1 is a summary of the information provided in log file 509of FIG. 5B. The various columns of Table 1 are defined as follows:

[0052] 1. “BRANCH” identifies each clock branch A-M;

[0053] 2. “EDGE” identifies whether the destination circuit changedstates in response to a rising (R) or falling (F) clock edge;

[0054] 3. “LOADS” lists the number of loads, or destination circuits,associated with a given clock branch;

[0055] 4. “LCOL,” for “left-column,” identifies the left-most column inlog file 540 that corresponds to a given clock branch;

[0056] 5. “RCOL,” for “right-column,” identifies the right-most columnin log file 540 that corresponds to a given clock branch;

[0057] 6. “MINΔ” lists the elapsed time between time CLK and the time atwhich the first load associated with a given clock branch changes state(i.e., the shortest signal-propagation delay from clock terminal CLK tothe output of a destination circuit on a given clock branch);

[0058] 7. “MAXΔ” lists the elapsed time between time CLK and the time atwhich the last load associated with a given clock branch changes state;and

[0059] 8. “MAX-MIN” is the difference between MINΔ and MAXΔ, andrepresents the clock skew for a given branch.

[0060] Reducing log file 509 into Table 1 provides a user with a simplemeans of analyzing the timing information provided in log file 509.TABLE 2 7777777777777777777788888888888888888899001122334455667788990011223344667788990005050505050505050505050505050505050505050000000000000000000000000000000000000000 A *-------* B * C *-* D *---* E*-* CLOCK F *----------* BRANCH G  *-------* H  *---* I *------* J *------------* K *------* L  *--------------------* M  *-*7777777777777777777788888888888888888899001122334455667788990011223344667788990005050505050505050505050505050505050505050000000000000000000000000000000000000000  TIME (picoseconds) -->

[0061] Table 2 graphically depicts a portion of the data provided by logfile 509. For each clock branch A-M, Table 2 shows time stamps—plottedas asterisks—associated with the first and last destination circuits toresponds to the clock signal on line CLK during the simulation of step508. These two extreme positions define the simulated clock skew for agiven clock branch. For example, the fastest destination circuit ofclock branch A responded in about 7600 ps, while the slowest destinationcircuit of clock branch A responded in about 8000 ps. Thus, clock branchA has a clock skew of 8000 ps minus 7600 ps, or 400 ps. Table 1 shows amore precise estimate of clock skew, and lists the clock skew of branchA as 370 ps.

[0062] Clock skew varies with supply-voltage and temperature and can bedifferent for rising and falling clock edges. Thus, some embodimentscollect four sets of data similar to that of Table 2: rising- andfalling-edge skew data for best- and worst-case voltage and temperatureconditions. In the example, the data of Table 2 is assumed to be theworst case skew data. The skew data for the three other sets ofconditions are omitted here for brevity.

[0063] Referring again to FIG. 5A, the next step 511 is to determinewhether the total clock skew is sufficiently short. A user can performstep 511 visually using the data of Tables 1 and 2. If the total skew issufficiently short, then the process moves to step 515, place and route.If, on the other hand, the total clock skew is too long, then the delayelements (e.g., delay element 410A-I) are modified to balance the clockbranches (step 512), as explained below.

[0064] The total estimated clock skew of clock tree 400 (FIG. 4) isapparent from Table 2. The fastest destination circuit is associatedwith clock branch C and responded in about 7,300 ps. The slowestdestination circuit is associated with clock branch L and responded inabout 8,850 ps. Thus, the overall clock skew of clock tree 400 isestimated to be about 8,850 ps minus 7,300 ps, or about 1,550 ps.

[0065] In an embodiment in which the clock-to-out time of thedestination circuits (flip-flops) for use with clock tree 400 is about1,500 ps, the total clock skew of clock tree 400 is preferablymaintained below 1,500 ps. This ensures that all of the destinationcircuits will operate with correct functional and timing relationships.Thus, the overall clock skew of 1,550 ps depicted in Table 2 isunacceptable, and will likely lead to a timing error. Clock branches A-Mshould therefore be adjusted to reduce the overall clock skew. Theprocess of FIG. 5A thus moves to step 512.

[0066] In step 512, netlist 505 is edited to change the delay associatedwith one or more of delay elements 410A-I. Referring to Table 2 above,the overall clock skew can be reduced, for example, by moving the delaysassociated with clock branches A, C, D, K, and M to the right (i.e.,increasing their delays). Referring back to FIG. 4, the delaysassociated with clock branches A, C, D, K, and M can be increased bymodifying delay elements 410A, 410D, 410F, and 410I. This can beaccomplished by adding or subtracting delay-inducing components, or bysubstituting delay elements for different components. Thesemodifications are made by editing netlist 510 to modify, remove, orreplace one or more hard library elements associated with delay elements410A-I. The stopper cells of delay elements 410A-I are not modified sothat the routing to and from the delay elements is preserved.

[0067] For illustrative purposes, increasing the delay induced by agiven delay element is assumed to add 250 ps of delay. Referring to FIG.4, adding 250 ps of delay to delay element 410A moves clock branches A-Jfive 50-picosecond places to the right, as compared with the data ofTable 2. Adding 250 ps of delay to delay element 410D moves clockbranches B and C an additional five places to the right, increasing thedelay of those branches by a total of 500 ps. Finally, adding 250 ps ofdelay to delay elements 410F and 410I moves each of clock branches K andM five places to the right.

[0068] Table 3 shows the skew data developed in steps 508 and 510 forclock tree 400 after increasing the delays associated with delayelements 410A, 410D, 410F, and 410I by 250 ps. TABLE 37777777777777777777788888888888888888899001122334455667788990011223344667788990005050505050505050505050505050505050505050000000000000000000000000000000000000000 A *-------* B * C  *-* D *---*E *-* CLOCK F  *----------* BRANCH G *-------* H *---* I  *------* J*------------* K  *------* L *--------------------* M *-*7777777777777777777788888888888888888899001122334455667788990011223344667788990005050505050505050505050505050505050505050000000000000000000000000000000000000000 TIME (picoseconds) -->

[0069] The foregoing delay adjustments reduced the total skew of clocktree 400 to the skew associated with clock branch L. That is, the totalclock skew is about 8,850-7,650=1,200 ps. The total clock skew of clocktree 400 was 1,550 ps before delay elements 410A-I were modified toreduce the skew. As discussed above, the maximum allowable clock skewwas assumed to be 1,500 ps, and so clock tree 400 was deemedunacceptable in step 511. However, the modifications of delay elements410A, 410B, 410D, 410F, and 410I reduced the total skew to an acceptable1,220 ps. Thus, the modified specification will now pass the test ofstep 511 and the process will move to step 515, place and route.

[0070] At step 515, a place and route tool is used to place and routenetlist 510. The particular paths between clock terminal CLK and eachdestination are automatically established through the respective delayelements by the place and route tool. Step 515 produces a circuitspecification 520 in the form of e.g. a CIF or GDSII Stream.

[0071] Specification 520 includes interconnect data. Timing simulationsof specification 520 consequently result in more accurate predictionsthan were achieved in step 508. Unfortunately, this means that netlist505 can have unacceptable skew even though passing the test of step 511.Specification 520 is therefore tested to determine whether the totalskew falls below the required minimum with routing in place.

[0072] In step 525, a delay calculator calculates the delays associatedwith the various signal paths defined by circuit specification 520,including each clock path defined between clock terminal CLK and adestination circuit. The delay calculator includes parameters specificto a particular fabrication recipe, and is therefore typically providedby the ASIC foundry employed to fabricate circuit specification 520. Thedelay calculator produces a delay file 530 (the Standard Delay Format,SDF, is widely used).

[0073] Circuit specification 520 provides a complete physicaldescription of integrated circuit 106 implemented in the targettechnology; delay file 530 provides the timing data for circuitspecification 520. Circuit specification 520 can therefore beback-annotated with the delay information in delay file 530 to simulatethe operation of the circuit design in the target technology.

[0074] In step 535, stimulus file 507 (created in step 506) is appliedto the circuit specification 520 back-annotated to include the delayinformation from delay file 530. The simulation results are then loggedas described above in connection with step 508 to create a new log file540. As compared with log file 509, log file 540 should be more accuratedue to the inclusion of better estimates of interconnect delays.

[0075] Log file 540 is simplified in the manner discussed above inconnection with step 510 to produce skew data 547. The format of skewdata 547 (not shown) is similar to the skew data of Tables 1 and 2, butthe data will be somewhat different due to the added precision providedby delay file 530.

[0076] The next step 550 is to determine, from skew data 547, whetherthe total clock skew is sufficiently short. If so, then netlistspecification 520 is deemed appropriate for fabrication and is thereforeoutput as a new circuit specification 555. If, on the other hand, thetotal clock skew is too long, then the delay elements are modified tobalance the clock branches (step 560), as explained above in connectionwith step 512. Stopper cells associated with the modified delay elementsserve as place holders to maintain the nets to and/or from the modifieddelay elements. The process then returns to step 515, place and route.

[0077] Conventional routing tools reroute nets associated withcomponents that are modified, removed, or replaced. Modifying delayelements to balance signal paths can therefore initiate a reroute thatintroduces new timing errors. The use of stopper cells (e.g., stoppercells 430 and 440 of FIG. 4) solves this problem. Each delay element isbounded on either or both ends by a stopper cell. The stopper cellsmaintain the nets to and/or from the delay elements so that modifying adelay element does not affect the routing to and from the delay element.The connections between stopper cells and modified delay componentswithin modified delay elements are rerouted. However, the netlistincludes regional constraints that instruct the place and route tool tomaintain the components within each delay element in close proximity tomaintain short connections between components. In one embodiment, theregional constraints are data assigning a heavy “weight” to thespecified connection. The netlist may also include routing constraintsthat instruct the router not to route through the delay elements topreserve die area in case additional area is needed for a delay-elementmodification. Regional and routing constraints are well understood inthe art.

[0078] The above process should eventually produce a specification 520that passes the test of step 550. If not, then conventional routingtechniques are employed to correct any remaining skew problems. Theresulting new specification 555 is then functionally tested usingconventional test vectors. If specification 555 passes these functionaltests, specification 555 is then used to fabricate the converted circuitdesign in the target technology.

[0079] In one embodiment, the invention is employed to convert a PLDcircuit design to a gate-array design. Logic circuits implemented ongate arrays are typically designed using libraries of pre-designed logicelements (e.g. multiplexers, flip-flops, and logic gates) known as“library elements,” typically defined using a number of more basicelements. The library elements are instantiated on rectangular areas ofsilicon, typically having the same height and different widths. Libraryelements fit together, like floor tiles, with groups of elements fittingtogether horizontally to form rows. The elements are connected togetherusing metal interconnect layers.

[0080] As discussed above, delay elements 410A-I are collections oflibrary elements. Clock tree 400 is balanced by reducing or increasingthe delays associated with the delay elements. To allow for suchadjustments, the library elements adjacent stopper cells in delayelements 410A-I are defined fairly large to preserve die area. Eachdelay element may then be modified, as needed, by altering the componentbounded by stopper cells. The delay of a given delay element can bereduced, for example, by replacing a large, slow buffer with a smaller,faster buffer, or can be increased by replacing a small, fast bufferwith a larger, slower buffer. Then, because the associated stopper cellsare not altered, subsequent routing steps retain the nets to and/or fromthe modified delay element.

[0081]FIG. 6 depicts four exemplary delay elements 601-604. Delayelements 601-604 include combinations of delay-inducing components 606extending from or between stopper cells 608. Delay-inducing components606 can be any circuit element, e.g., a buffer or inverter, that inducesan appropriate delay into the signal path of interest. A stopper cellcan be any circuit component inserted into a netlist and labeled in sucha way as to prevent the component from being modified, and therefore topreserve a routed connection to and/or from the stopper cell.

[0082] Each stopper cell and delay element introduces some delay intothe associated signal path. In some cases, this delay should be as smallas possible. For example, where the delay associated with a given signalpath should be minimized to reduce skew, or where a stopper cell isrequired to force a place-and-route tool to route a given signal througha predetermined physical location. In such situations, the presentinvention employs a novel stopper cell that occupies very little areaand introduces a minimal amount of delay.

[0083]FIG. 7A depicts one embodiment of a stopper cell 700 that has aminimal impact on die area and signal propagation delay. Stopper cell700 is a library element that defines a conductive segment 705 used tohold the place of a selected line segment, and is depicted graphicallyas wire segment 705 extending between a pair of ports 710 and 715.Conductive segment 705 does not connect to any active circuit componentswithin the bounds of stopper cell 700.

[0084]FIG. 7B depicts an example of how stopper cell 700 is physicallyinstantiated in a gate array. In addition to the elements described inconnection with FIG. 7A, stopper cell 700 conventionally includes a pairof power conductors V_(DD) and V_(SS) for conveying power-supplyvoltages through stopper cell 700. The following is a LEF textspecification of stopper cell 700. LEF, for “library exchange format, isa common industry standard format. Ports 710 and 715 allow stopper cell700 to connect to other cells. # # HOLE is the cut layer between metal-1and metal-2 # CT is the via between field and metal-1 through CONT (cutlayer) # # # ADDED VIA AD for METAL 1 ACCESS PIN VIA AD # RESISTANCE0.4; | LAYER ALA; RECT −1.2 −1.2 1.2 1.2; # LAYER HOLE ; | --> can beused to create # RECT −0.5 −0.5 0.5 0.5; | Metal 2 accessible pin #LAYER ALB; | # RECT −1.2 −1.2 1.2 1.2; | END AD # MACRO WSTP CLASS CORE; FOREIGN WSTP −1.8 −1.8 ; SIZE 18.0 BY 50.4 ; SITE BCP 0 0 N DO 1 BY 1STEP 14.4 50.4 ; SITE BCN 0 25.2 N DO 1 BY 1 STEP 14.4 50.4 ; ORIGIN 1.81.8 ; PIN A DIRECTION INPUT ; USE SIGNAL ; PORT LAYER ALA ; VIA 3.6 25.2AD ; END END A PIN X DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER ALA ;VIA 10.8 25.2 AD ; END END X PIN VDD DIRECTION INOUT ; USE POWER ; SHAPEABUTMENT ; PORT LAYER ALA ; WIDTH 2.4 ; PATH 0.0 10.8 14.4 10.8 ; VIA0.0 10.8 CT ; VIA 7.2 10.8 CT ; VIA 14.4 10.8 CT ; END END VDD PIN VSSDIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER ALA ; WIDTH2.4 : PATH 0.0 36.0 14.4 36.0 ; VIA 0.0 36.0 CT ; VIA 7.2 36.0 CT VIA14.4 36.0 CT END END VSS OBS LAYER ALA ; PATH 3.6 25.2 END END WSTP

[0085] The simplicity of stopper cell 700 allows stopper cell 700 to bemade very small, thus minimizing the die area required to maintain thephysical location of a given line segment. Other stopper cells can beused as place holders in optimizing networks in accordance with theinvention. For example, buffers, inverters, or multiplexers can also bestopper cells.

[0086] Stopper cell 700 is faster than conventional library elementsbecause stopper cell 700 is not logic. Stopper cell 700 is essentially alibrary element in which the defined component is a conductor. Asdiscussed above, stopper cell 700 can be added to a netlist to force aplace-and-route tool to route a signal through a specified physicallocation on a die. Further, stopper cell 700 can be adapted to force aselected signal path to change metal layers, from layer one to layer twoin a two-layer metalization process, for example.

[0087]FIG. 7C depicts a stopper cell 720 in accordance with anotherembodiment of the invention. Stopper cell 720 is similar to stopper cell700 of FIG. 7B, but includes a conductive segment 725 that joins a pairof ports 730 and 735 at a 45-degree angle. Stopper 720 may be used, forexample, to join horizontal and vertical routing segments. For moreinformation on stopper cells for use in accordance with the invention,see U.S. Pat. No. 6,308,309 entitled “Place-holding Library Elements forDefining Routing Paths,” by Andy Gan and Glenn A. Baxter, issued Oct.23, 2001, which is incorporated herein by reference.

[0088] While the present invention has been described in connection withspecific embodiments, variations of these embodiments will be obvious tothose of ordinary skill in the art. For example,

[0089] 1. while the present invention is illustrated using exemplaryclock trees, the invention is also applicable to other types of signalpaths, such as data paths;

[0090] 2. in another embodiment, the individual clock branches arealigned by finding and plotting the mean destination delay for eachbranch. The branch delays are then altered, as discussed above, to alignthe timing of the mean delay values.

[0091] Moreover, some components are shown directly connected to oneanother while others are shown connected via intermediate components. Ineach instance the method of interconnection establishes some desiredelectrical communication between two or more circuit nodes (e.g., linesor terminals). Such communication may often be accomplished using anumber of circuit configurations, as will be understood by those ofskill in the art. Therefore, the spirit and scope of the appended claimsshould not be limited to the foregoing description.

What is claimed is:
 1. A signal distribution network on an integratedcircuit, the network comprising:
 1. a network input node adapted toreceive signal transitions;
 2. a stopper cell including:
 1. an inputport connected to the network input node and having a first minimumdimension in a plane parallel to a surface of the integrated circuit; 2.an output port; and
 3. a conductor connected between the input port andthe output port, the conductor having a second minimum dimension in theplane parallel to the surface of the integrated circuit;
 4. wherein thefirst minimum dimension is greater than the second minimum dimension;and
 3. a destination circuit having an input terminal connected to thestopper-cell output port.
 2. The network of claim 1, wherein the stoppercell further comprises:
 1. a second conductor adapted to convey a firstpower-supply voltage through the stopper cell; and
 2. a third conductoradapted to convey a second power-supply voltage through the stoppercell.
 3. The network of claim 2, wherein the input port and the outputport are in between the second and third conductors.
 4. The network ofclaim 2, wherein the stopper cell does not include an active circuitcomponent.
 5. The network of claim 1, wherein the network is a clockdistribution network.
 6. The network of claim 1, wherein the integratedcircuit is a mask-programmed integrated circuit.
 7. The network of claim1, further comprising a second stopper cell having an input portconnected to the output port of the first stopper cell.
 8. The networkof claim 7, further comprising a delay-inducting component connectedbetween the first and second stopper cells.